(1) Field of the Invention
The present invention relates to a method of forming polysilicon gates, and in particular, to a method of controlling the critical dimension width of a polysilicon gate by using very thin lithographic layers in a micro-patterning process.
(2) Description of the Related Art
Micro-lithography used in the very large (VLSI) or ultra large (ULSI)scaling of integrated circuits requires high dimensional control to produce device feature sizes over the entire wafer surface with high accuracy and precision. A first step in a lithographic process is the forming of a photoresist layer over features on a substrate and then the patterning of the photoresist by exposing it through a photomask. The thickness of the photoresist layer determines to a large extent the resolution required to print minimum size images, and in order to build devices with submicron features, lithographic processes with submicron resolution capabilities are needed. It is disclosed in the present invention a method to form very thin lithographic layers to achieve polysilicon width dimensions less than 0.25 micrometers (.mu.m) reaching 0.18 .mu.m using i-line and KrF lithography, respectively.
When a photoresist layer is formed over features on a substrate, its thickness varies across the substrate depending upon the size and geometry of the underlying features. That is, as the resist film crosses over steps or indentations underneath, its much thinner over the top of steps than over regions which are low-lying. During the exposure, either the thin resist becomes overexposed, or the thicker resist underexposed. Upon development, a resist pattern crossing a step will therefore possess a linewidth various (i.e., narrower on the top of the step). For lines in which step heights approach the size of the linewidth (e.g., for sub-micron linewidths), such variations in dimension become intolerable. In addition, standing wave effects in thick resist layers reduces their minimum resolution. Finally, reflective substrates also degrade resolution in thick resist films. (See Wolf, S., and Tauber, R. N. "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, Calif., 1990, pp.438-439).
Such dimensional variation effects caused by substrate topography can be seen in prior art. FIG. 1 shows a portion of a partially completed integrated circuit in which there is a silicon substrate (10). Field oxide regions (12) are formed in and on the silicon substrate resulting in a uneven topography of the top surface of the substrate. A gate oxide layer (14) is grown on the surface of the substrate and the field oxide regions. A layer of polysilicon (16) is deposited over the gate oxide layer. A layer of photoresist (18) covers the surface of the substrate and planarizes the substrate. It will be apparent to those skilled in the art that the differing photoresist depths A and B will make an imperfect image and resulting imperfect image and resulting mask, causing critical dimension variation. Due to the standing-wave phenomenon, different resist thicknesses result in different resist dimensions; this is known as the swing-effect. Also, the polysilicon on the sloped edge of the field oxide region reflects light (20) during photolithographic exposure, resulting in necking.
FIG. 2 shows the integrated circuit chip after photolithography and etching with completed polysilicon lines (16A), (16B), and (16C). FIG. 3 shows a top view of FIG. 2, including field oxide regions (12), active areas (22), and polysilicon lines (16A), (16B), and (16C) . The mask used has the same dimensions for polysilicon lines (16A) and (16B), but different dimensions are printed on the photoresist mask because of the different photoresist thicknesses on the topography. Resulting polysilicon line (16A) has a different dimension than polysilicon line (16B) because of the photoresist thickness difference (A) and (B) in FIG. 1 due to different elevations. This figure also illustrates the necking problem (24) in polysilicon line (16C), especially for areas having a large change in topography such as the field oxide to active areas. This necking problem could result in early breakdown of the integrated circuit via the neck, (24).
U.S. Pat. No. 5,324,689 to Yoo shows a method of critical dimension control with a planarized underlayer. The mask comprises: polysilicon/spin-on-glass (SOG)layer/photoresist. The photoresist layer is exposed through the desired mask, developed and patterned to form the desired resist mask. The exposed SOG and polysilicon are removed by etch. The photoresist mask is stripped. The SOG layer remaining over the polysilicon patterned layer is removed, resulting in the polysilicon layer having the desired uniform critical dimension. In another U.S. Pat. No. 5,45,588, Yoo also shows a method of using a disposable hard mask for gate dimension control.
Abernathy, on the other hand, in U.S. Pat. No. 5,219,788, uses bilayer metallization cap for photolithography. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO.sub.2. The barrier layer may also be a thin coating of SOG. The barrier layer prevents interaction between the titanium nitride and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed. Kim, in U.S. Pat. No. 5,354,713 shows a method of a contact of a multi-layered metal line of a highly integrated semiconductor device. The insulating layer between the metal lines is flattened an step coverage is improved by using a SOG layer or polyimide. This invention discloses a different micro-patterning process where thin multiple masks are used in order to achieve tighter control on dimensions so as to be able to form features of sizes less than 0.25 micrometers (.mu.m) to 0.18 .mu.m.